SXoM-C5

System-on-a-Chip (SoC)

SoM compliant with SMARC 1.1 specification

SXoM-C5 is a complete System-on-Module (SoM)

compliant with the SMARC (Smart Mobility ARChitecture) 1.1 specification by SGET.
The board is designed to function as the system core of modular platforms for
high-performance DSP applications.

Low Power
SMARC

The core of SXoM-C5 is an Altera Cyclone V SoC (System-on-a-Chip)

that combines a Cyclone V FPGA fabric featuring up to 110K logic elements with an ARM-based dual-core hard processor system running at up to 925 MHz.

Applications

+ Motion capturing & analysis
+ Medical & scientific imaging
+ Security and surveillance
+ High-end machine vision
+ Traffic monitoring
+ Airborne imaging

SXoM-C5

+ Low-power embedded architecture
+ High-performance data processing
+ Ultra-compact form factor: 82 mm x 50 mm
+ System-on-Module compliant with
   SMARC 1.1 specification by SGET

+ Powered by Altera Cyclone V SX SoC 5CSX C2/C4/C5/C6 (customer-specific)
+ Cyclone V FPGA fabric
+ ARM-based hard processor system
+ Up to 16 Gb DDR3 SDRAM ×32 bit (CPU)
+ Up to 16 Gb DDR3 SDRAM ×32 bit (FPGA)


+ Altera Cyclone V FPGA fabric
+ 25K – 110K logic elements
+ 1.4 – 5.6 Mb block memory
+ 36 – 112 DSP blocks

 


+ Dual-core ARM Cortex™-A9 MPCore™ processor, 700 – 925 MHz clock frequency
+ 4,625 DMIPS (Dhrystone 2.1) at 925 MHz (two cores)
+ 32 KB of L1 instruction cache and 32 KB of L1 data cache per processor
+ 512 KB of shared L2 cache
+ 64 KB of on-chip RAM

 

Block Diagram & Interfaces


Designed as System Core for Modular DSP Platforms

+ Flexible heterogeneous many-core architecture
+ Ideal for real-time high-performance image processing and analysis tasks
+ FPGA and embedded software framework in development

Compatible Evaluation Carrier Boards

+ Any SMARC-compliant evaluation carrier board
+ ADLINK LEC-BASE
   SMARC Reference Carrier Board
+ Advantech ROM-DB5900
   Development Board for SMARC v1.1 RISC Module